1. Background Art
In the non-volatile memory device disclosed in paragraphs [0009] of [0021] of Japanese Kokai Publication No. JP 2001-176290 (Patent Document 1), at the time of power-up by a power supply, initial setting data in an initial setting data region provided within a memory cell array is latched in a data latch circuit. Specifically, as shown in FIG. 11, upon detection of power-on, power-on-reset is effected (S110), and a ready/busy signal (R/B) is set to a busy state (S130) after a predetermined waiting time (S120). Then, defective address data, control voltage value data and other initial setting data are read and set (S140 to S160). Upon completion of reading out all of initial setting data, R/B is set to a ready state (standby state) (S170). The busy state of R/B allows external notification of access inhibition.
The initial setting operation from the detection of power-on to latching initial setting data in the data latch circuit is programmed in a control circuit that controls the writing and erasing operation in advance so that the initial setting operation is automatically controlled in response to the power-on. Upon starting the control circuit, the initial setting data is read out from a decode circuit and a sense amplifier circuit as with regular data readout.
Also, paragraphs [0008] to [0010] of Japanese Kokai Publication No. JP 2003-178589 (Patent Document 2) disclose operations similar to Patent Document 1. It is assumed that the initial setting data is read, in addition to the operation of Patent Document 1, on the basis of an internal clock that is generated in the interior of the chip. When the internal clock is not adjusted by trimming data for canceling process variations, a variation in the cycle becomes large. In the case where the cycle is varied toward a long cycle side, a waiting time is lengthened. In view of this problem, clock cycle adjustment data for adjusting a clock cycle that is generated by a clock generator circuit is first read out among the initial setting data after power-up. Then, the clock cycle generated by the clock generator circuit is adjusted. After completion of this adjustment, remaining initial setting data is read out. That is, Patent Document 2 discloses that the remaining initial setting data is read out on the basis of an operation clock that is adjusted on the basis of the clock cycle adjustment data. Patent Document 1, as well as Patent Document 2, provides external notification of the access inhibition according to the busy state of R/B until after reading out and setting defective address data S6, control voltage value data S7 and other initial setting data S8.
Finally, Japanese Kokai Publication No. JP S60-205428 (Patent Document 3) provides additional relevant prior art disclosures.
2. Problems to Be Solved by the Invention
In Patent Documents 1 and 2, the busy state of the ready/busy signal R/B which inhibits external access is outputted until all of the initial setting data is latched in the data latch circuit when the power turns on, thereby preventing improper external access if initial setting is not completed.
However, the initial setting data of a non-volatile memory device includes, for example, setting information of circuit constants for various operations, as well as setting information of redundant addresses that relieves defective memory cell issues, and setting information for a write protect function such as information on whether writing in a given memory region which is represented by a sector is permissible or not. The number of the initial setting data will increase for larger capacities of non-volatile memory devices. This means that the required time for reading out the initial setting data from the initial setting data region and latching the initial setting data in the data latch circuit at the time of power-up will increase. Also, for storing larger amounts of initial setting data, it is expedient that one area of a memory cell array that is a region in which regular data is stored is allocated as an initial setting data area.
Regular access operation cannot be utilized on the memory array while the initial setting data is read out from the initial setting data area that is disposed in one area of the memory cell array, and the busy state will be maintained for longer periods of time as the initial setting data increases. As a result, there arises a problem that a great period of time may be required for initial setting at the time of power-up.
In particular, in the case where the non-volatile memory device is incorporated into a system, and boot programs or application programs at the time of starting the system are stored therein, there arises a problem that the period of time required for the boot program to start after the power-up, or until the application program starts after the power-up, may be long.